1. Field of the Invention
The present invention relates, in general, to a method for the analysis of defects in a semiconductor device and, more particularly, to a method for examining a semiconductor device accurately, rapidly and in three dimensions.
2. Description of the Prior Art
When a semiconductor device is made highly integrated, the layer thickness and the line width in the semiconductor device become are reduced. This reduction generates misalignments among polysilicon layers, causing shorts in the polysilicon layers.
Conventionally, to examine the defects of a device caused by the misalignment generated in the polysilicon layers, the layers formed in the device are removed one by one with a dry or a wet etch process and the state of each layer is observed. Alternatively, there has been employed a lapping method, in which, using a bit map, a region including the portion at which a defect is believed to be generated is cut with a diamond pencil and then, while the region is abraded finely,,the state of the region abraded is observed to find the defective portion.
The conventional methods may be useful in observing a short generated in the same layer. However, since, in a structure in which layers overlap with one another in three dimensions, an upper layer spaced out by a minute distance screens lower layers, and the state between the lower layers can not be, in two dimensions, observed with the conventional methods. Accordingly, after removing the upper layer, the trace of contact left on the lower layer and the dimension of the lower layer are observed, so as to indirectly analyze the state of a defect.
Particularly, when the lapping method is used, the preparatory procedure for the analysis is troublesome. In addition, since the physical strength required in the lapping method may damage the pattern formed in the device, it is inferior in an accuracy aspect.